Update for v2, fixes post v1 manufacture
* Connect input header CV/GATE rails to the bus, this makes it possible to chain boards into the same bus using the existing headers on the output header. * Move the via's for the +12V rail to the tile power connections so it doesn't cross most of the GND signal path on the top ground plane.
This commit is contained in:
parent
a7ef86eb4e
commit
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12
eagle.epf
12
eagle.epf
@ -274,7 +274,7 @@ UsedLibrary="/Users/benie/Documents/EAGLE/libraries/tsyklon-labs.lbr"
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File="power bus.brd"
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PadDrills=" 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6"
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@ -312,13 +312,13 @@ SwapLevel=0
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Layer=1
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[Win_2]
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Type="Schematic Editor"
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File="power bus.sch"
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PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
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PadDrills=" 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6"
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@ -334,7 +334,7 @@ DimensionExtWidths=" 0.127 0.254 0.1 0.13 0.26 0"
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@ -357,7 +357,7 @@ ArcDirection=0
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[Win_3]
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@ -365,7 +365,7 @@ Type="Control Panel"
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[Desktop]
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Screen="1440 900"
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@ -153,7 +153,7 @@
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@ -1926,7 +1926,7 @@ design rules under a new name.</description>
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<vertex x="0" y="0"/>
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@ -1980,28 +1980,24 @@ design rules under a new name.</description>
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@ -2073,6 +2069,14 @@ design rules under a new name.</description>
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@ -2098,6 +2102,14 @@ design rules under a new name.</description>
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@ -11290,6 +11290,16 @@ Source: www.kingbright.com</description>
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<segment>
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@ -11347,6 +11357,16 @@ Source: www.kingbright.com</description>
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<segment>
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<segment>
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<net name="N$1" class="0">
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<segment>
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